Tap stabilizer method and structure for coherent optical receiver

ABSTRACT

A method and structure for a coherent optical receiver device. Timing recovery (TR) is implemented after channel dispersion (i.e., chromatic dispersion (CD) and polarization mode dispersion (PMD)) compensation blocks. This architecture provides both improves performance and reduces power consumption of the device. Also, a TR loop is provided, enabling computing, by an error evaluation module, a first sampling phase error (SPE) and computing, by a timing phase information (TPI) module coupled to the error evaluation module, a second SPE from a plurality of CD equalizer taps PMD equalizer taps. The first and second SPE are combined into a total phase error (TPE) in a combining module, and the resulting TPE is filtered by a timing recovery (TR) filter coupled to an interpolated timing recovery (ITR) module and the combining module. The ITR module then synchronizes an input signal of the coherent optical receiver according to the TPE.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application claims priority to and is a continuation of U.S. application Ser. No. 16/134,722, filed Sep. 18, 2018, which is a continuation of U.S. application Ser. No. 15/792,396, filed Oct. 24, 2017, now issued as U.S. Pat. No. 10,110,319 on Oct. 23, 2018, which claims priority to an incorporates by reference, for all purposes, the following U.S. provisional patent applications: U.S. Provisional App. No. 62/412,052, filed on Oct. 24, 2016; U.S. Provisional App. No. 62/412,071, filed on Oct. 24, 2016; U.S. Provisional App. No. 62/412,033, filed on Oct. 24, 2016; U.S. Provisional App. No. 62/412,047, filed on Oct. 24, 2016; U.S. Provisional App. No. 62/412,015, filed on Oct. 24, 2016; U.S. Provisional App. No. 62/412,002, filed on Oct. 24, 2016; and U.S. Provisional App. No. 62/412,039, filed on Oct. 24, 2016. The present application also incorporates by reference, for all purposes, the following U.S. Patents: U.S. Pat. No. 9,337,934, filed on Nov. 29, 2013, and issued on May 10, 2016; U.S. Pat. No. 9,178,625, filed on Dec. 3, 2013, and issued on Nov. 3, 2015; and U.S. Pat. No. 9,077,572, filed on Jan. 17, 2013, and issued on Jul. 7, 2015.

BACKGROUND OF THE INVENTION

The present invention relates to communication systems and integrated circuit (IC) devices. More particularly, the present invention provides for improved methods and devices for optical communication.

Over the last few decades, the use of communication networks exploded. In the early days Internet, popular applications were limited to emails, bulletin board, and mostly informational and text-based web page surfing, and the amount of data transferred was usually relatively small. Today, Internet and mobile applications demand a huge amount of bandwidth for transferring photo, video, music, and other multimedia files. For example, a social network like Facebook processes more than 500 TB of data daily. With such high demands on data and data transfer, existing data communication systems need to be improved to address these needs.

Optical communication is one major technological area that is growing to address these high demands on data. Optical communication systems typically communicate data over a plurality of channels corresponding to different phases and/or polarizations of the optical signal. While the data communicated over the different channels is typically aligned relative to a common clock when transmitted by the transmitter, delay (or skew) may be introduced into one or more of the channels based on characteristics of the transmitter, receiver, and/or the optical fiber. As a result, the relative timing of the data in the various channels may be misaligned at the receiver, causing degradation of the recovered data.

Although there are several types of devices and methods related to optical communication systems, they have been inadequate for the advancement of various applications. Conventional embodiments consume large areas or large amounts of power and suffer from performance limitations. Therefore, improved devices and methods for optical communication systems and related electronics are highly desired.

BRIEF SUMMARY OF THE INVENTION

The present invention relates to communication systems and integrated circuit (IC) devices. More particularly, the present invention provides for improved methods and devices for optical communication.

The present invention provides for the TR operation after channel dispersion compensation blocks (e.g., for chromatic dispersion (CD) and polarization mode dispersion (PMD)). This architecture provides both improves performance and reduces power consumption of the receiver device. Performance is improved because channel impairments (e.g., high order PMD, residual CD, very low excess bandwidth, etc.) do not impact the TR operation. The latency of the TR loop is not affected since the feed-forward equalization (FFE) equalizer is not included within the TR loop. Power consumption is reduced because the use of the FFE immediately after the bulk chromatic dispersion (BCD) equalizer, which enables residual CD and PMD to be jointly compensated in only one frequency-domain (FD) equalizer. Using a frequency domain block least-means-square (LMS) adaptation reduces the complexity of the device architecture. Further, baud rate timing recovery algorithms, such as Muller and Mueller (M&M) can be adopted. Thus, in an example, the present invention adopts an asynchronous FD adaptive equalizer to implement timing recovery with equalized signals, and to reduce implementation complexity.

In various examples, the present invention provides for a method and structure for a coherent optical receiver device. The device can include an input signal; a first fast Fourier transform (FFT) module receiving the input signal, the first FFT module being configured to compute a first discrete Fourier transform (DFT) of the input signal; a chromatic dispersion (CD) equalizer module coupled to the first FFT module, the CD equalizer module being configured to compensate for CD affecting the input signal; a polarization mode dispersion (PMD) equalizer module coupled to the CD equalizer and a least means square (LMS) module, the PMD equalizer module being configured to compensate for PMD affecting the input signal following compensation by the CD equalizer module. The PMD equalizer module includes a plurality of PMD taps. In a specific example, the CD equalizer module includes a non-adaptive frequency-domain (FD) equalizer, and the PMD equalizer module includes an adaptive FD equalizer. Further, the input can be a dual polarization input with an x-type and y-type inputs.

In an example, the device can also include an inverse FFT (IFFT) module coupled to the PMD equalizer module, the IFFT module being configured to compute an inverse DFT of the input signal; an interpolated timing recovery (ITR), slicer, and error evaluation module coupled to the IFFT module. The ITR, slicer, and the error evaluation can be separate modules, the ITR module being configured to retime the input signal, the slicer module being configured to derive the data stream, and the error evaluation module being configured to retime the input signal.

In an example, the device can include a zero padding module coupled to the slicer and error evaluation module, the zero padding module being configured to increase a sampling rate of the input signal; and a second FFT module coupled to the zero padding module, the second FFT module being configured to compute a second DFT of the input signal. In an example, the LMS module is coupled to the second FFT module, the CD equalizer module, and the PMD equalizer module. The LMS module outputs to the PMD equalizer module and is configured to filter the input signal.

In an example, the PMD equalizer is coupled to an ITR module. In a specific example, the IFFT module is configured between the PMD equalizer module and the ITR module. An error evaluation or error computation module is coupled to the ITR module. The error evaluation module can be configured to compute a first sampling phase error (SPE). The device also includes a timing phase information (TPI) module, a combining module, and a timing recovery (TR) filter. The TPI module can be coupled to the PMD equalizer module or to an IFFT module that is coupled to the PMD equalizer module (as described for the ITR module). The TPI module can be configured to compute a second SPE from the plurality of PMD taps from the PMD equalizer module. Then, the combining module can combine the first SPE and the second SPE into a total phase error (TPE). The TR filter can filter the TPE to be used by the ITR module to synchronize the input signal.

The method includes computing, by the error evaluation module, a first sampling phase error (SPE) and computing, by a timing phase information (TPI) module, a second SPE from a plurality of chromatic dispersion (CD) equalizer taps and polarization mode (PMD) equalizer taps. The first and second SPE are combined into a total phase error (TPE) in a combining module, and the resulting TPE is filtered by the TR filter coupled to an ITR module and the combining module. The ITR module then synchronizes an input signal of the coherent optical receiver according to the TPE. Those of ordinary skill in the art will recognize other variations, modifications, and alternatives.

A further understanding of the nature and advantages of the invention may be realized by reference to the latter portions of the specification and attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more fully understand the present invention, reference is made to the accompanying drawings. Understanding that these drawings are not to be considered limitations in the scope of the invention the presently described embodiments and the presently understood best mode of the invention are described with additional detail through the use of the accompanying drawings in which:

FIG. 1 is a simplified diagram illustrating a block diagram of a coherent optical receiver according to an example of the present invention.

FIG. 2 is a simplified diagram illustrating a block diagram of a portion of a coherent optical receiver according to an example of the present invention.

FIG. 3A-3D are simplified graphs illustrating simulations for a coherent optical receiver according to conventional example.

FIG. 4A-4D are simplified graphs illustrating simulations for a coherent optical receive according to an example of the present invention.

FIG. 5A-5D are simplified graphs illustrating simulations for a coherent optical receiver according to conventional example.

FIG. 6A-6D are simplified graphs illustrating simulations for a coherent optical receive according to an example of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to communication systems and integrated circuit (IC) devices. More particularly, the present invention provides for improved methods and devices for optical communication.

The following description is presented to enable one of ordinary skill in the art to make and use the invention and to incorporate it in the context of particular applications. Various modifications, as well as a variety of uses in different applications will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not intended to be limited to the embodiments presented, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without necessarily being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.

The reader's attention is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. All the features disclosed in this specification, (including any accompanying claims, abstract, and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

Furthermore, any element in a claim that does not explicitly state “means for” performing a specified function, or “step for” performing a specific function, is not to be interpreted as a “means” or “step” clause as specified in 35 U.S.C. Section 112, Paragraph 6. In particular, the use of “step of” or “act of” in the Claims herein is not intended to invoke the provisions of 35 U.S.C. 112, Paragraph 6.

Please note, if used, the labels left, right, front, back, top, bottom, forward, reverse, clockwise and counter clockwise have been used for convenience purposes only and are not intended to imply any particular fixed direction. Instead, they are used to reflect relative locations and/or directions between various portions of an object.

Clock timing recovery (TR) critical for data communications, and optical data communications are no exception. Certain conventional devices implement timing recovery operations with intersymbol interference (ISI)-free samples. However, there is an interaction problem between timing synchronization and equalization in coherent optical applications. A high higher of multiplications and oversampling is required by squared or fourth-power based TR algorithms, which leads to increased power consumption. Examples of the present invention address this problem with a receiver architecture based on asynchronous frequency domain equalization.

In an example, the present invention provides for the TR operation after channel dispersion compensation blocks (e.g., for chromatic dispersion (CD) and polarization mode dispersion (PMD)). This architecture provides both improves performance and reduces power consumption of the receiver device. Performance is improved because channel impairments (e.g., high order PMD, residual CD, very low excess bandwidth, etc.) do not impact the TR operation. The latency of the TR loop is not affected since the feed-forward equalization (FFE) equalizer is not included within the TR loop. Power consumption is reduced because the use of the FFE immediately after the bulk chromatic dispersion (BCD) equalizer, which enables residual CD and PMD to be jointly compensated in only one frequency-domain (FD) equalizer. Using a frequency domain block least-means-square (LMS) adaptation reduces the complexity of the device architecture. Further, baud rate timing recovery algorithms, such as Muller and Mueller (M&M) can be adopted. Thus, in an example, the present invention adopts an asynchronous FD adaptive equalizer to implement timing recovery with equalized signals, and to reduce implementation complexity.

FIG. 1 is a simplified diagram illustrating a block diagram of a coherent optical receiver according to an example of the present invention. As shown, device 100 can include an input signal; a first fast Fourier transform (FFT) module receiving the input signal, the first FFT module 111 being configured to compute a first discrete Fourier transform (DFT) of the input signal; a chromatic dispersion (CD) equalizer module 120 coupled to the first FFT module 111, the CD equalizer module 120 being configured to compensate for CD affecting the input signal; a polarization mode dispersion (PMD) equalizer module 130 coupled to the CD equalizer and a least means square (LMS) module 180, the PMD equalizer module 130 being configured to compensate for PMD affecting the input signal following compensation by the CD equalizer module. The PMD equalizer module 130 includes a plurality of PMD taps. In a specific example, the CD equalizer module includes a non-adaptive frequency-domain (FD) equalizer, and the PMD equalizer module includes an adaptive FD equalizer. Further, the input can be a dual polarization input with an x-type and y-type inputs.

In an example, the device can also include an inverse FFT (IFFT) module 140 coupled to the PMD equalizer module 130, the IFFT module being configured to compute an inverse DFT of the input signal; an interpolated timing recovery (ITR), slicer, and error evaluation module 150 coupled to the IFFT module 140. The ITR, slicer, and the error evaluation can be separate modules, the ITR module being configured to retime the input signal, the slicer module being configured to derive the data stream, and the error evaluation module being configured to retime the input signal. Further details are provided in reference to FIG. 2.

In an example, the device can include a zero padding module 160 coupled to the slicer and error evaluation module 150, the zero padding module 160 being configured to increase a sampling rate of the input signal; and a second FFT module 170 coupled to the zero padding module 160, the second FFT module 170 being configured to compute a second DFT of the input signal. In an example, the LMS module 180 is coupled to the second FFT module 170, the CD equalizer module 120, and the PMD equalizer module 130. The LMS module 180 outputs to the PMD equalizer module 130 and is configured to filter the input signal. Those of ordinary skill in the art will recognize other variations, modifications, and alternatives.

The reduction of complexity results from not having to use separate FD BCD and FFE equalizers. As shown in FIG. 1, only one (dual polarization) FFT and only one (dual polarization) IFFT are required in the signal path. An architecture using separate FD blocks for the BCD and FFE requires extra FFTs and IFFTs as a result of going back and forth from the frequency domain to the time domain. Further, the LMD update can be viewed as computing a correlation between the input signal and the error. Here, this correlation is computed in the frequency domain, which reduces complexity the same way as in convolution computations.

With this architecture, an interaction problem arises when TR is achieved after the adaptive equalizer (i.e., PMD equalizer). This problem occurs because the adaptation algorithm of the equalizer and the timing-synchronizer use the same (equalized) signal as their input. The equalizer tries to compensate the misadjustment of the discrete time impulse response due to the sampling phase error, while the TR tries to equalize the distortion of the impulse response by changing the sampling phase. As a consequence, the timing phase and the equalizer taps are drifting. Conventional solutions to this problem have severe drawbacks in (time variant) coherent optical channels. Making the timing loop much faster than the equalizer can mitigate this interaction problem, but the timing phase may still drift slowly over long periods of time.

According to an example of the present invention, a constrained adaptive algorithm can be used to reduce or eliminate strong interaction between the adaptive equalizer and the timing recovery loop. Constraining multiple equalizer taps can be done if the adaptive filter is known to have a certain characteristic (e.g., linear phase implies tap symmetry). A constrained adaptive algorithm can also be applied in which the magnitude and the phase responses of the adaptive equalizer remain unchanged at a given frequency. Timing phase information (TPI) contained within the equalizer taps can also be fed into the timing recovery loop as a factor for computing sampling phase error.

FIG. 2 is a simplified diagram illustrating a block diagram of a portion of a coherent optical receiver according to an example of the present invention. As shown, device 20 includes a PMD equalizer module 210, which is similar to the PMD equalizer module 130 of FIG. 1. This PMD equalizer is coupled to an ITR module 220. In a specific example, an IFFT module (such as IFFT module 140 of FIG. 1) is configured between the PMD equalizer module 210 and the ITR module 220. The ITR module is configured to synchronize the input signal according to a tap stabilizing algorithm.

Let c be the impulse response of the equalizer and τ_(n) be the timing error. Assuming that the timing error is small, the equalizer impulse response in the presence of timing error can be expressed as a linear function of the timing error τ_(n) as follows: c(E(τ_(n)))=S _(c) E(τ_(n))+C _(τ=0) where s_(c) is the vector of the slope of the equalizer coefficients and E(τ_(n)) comes from the averaging of the equalizer loop.

Since the TR loop is achieved after the adaptive equalizer, its timing function will be modified as a result of the variation of the equalizer coefficients. If c_(τ=0) is available, it is possible to extract the mean timing error by adding a new timing-error signal obtained from the equalizer taps as follows: s _(c) E(τ_(n))=c(E(τ_(n)))−c _(τ=0) This approach requires a priori knowledge of the particular equalizer coefficients at an optical timing phase (c_(τ=0)).

In an example, the present tap stabilizer algorithm can be used to obtain sampling phase information based on the response of an multiple input multiple output (MIMO) FFE. The algorithm can use the Jones matrix because it is unitary, its determinant is independent of the fiber impairments (i.e., DGD, second order PMD (SOPMD)), and contains information of the timing error. This scheme is able to provide reliable information even in the presence of highly dispersive channels. Furthermore, this scheme is able to work with any roll-off factor and can be applied to blind adaptation procedures.

The channel transfer matrix at the FFE input can be written as follows: H(ω)=G(ω)J(ω) where the scalar linear factor G (ω) represents the total response of the transmit pulse, residual CD, and receive pulse, while J(ω) is the PMD Jones unitary matrix (i.e., det{J(ω)}=1) given by the following:

${J(\omega)} = \begin{bmatrix} {U(\omega)} & {V(\omega)} \\ {- {V^{*}(\omega)}} & {U^{*}(\omega)} \end{bmatrix}$

The determinant of the channel transfer matrix is as follows: det{H(ω)}=G ²(ω)det{J(ω)}=G ²(ω) Here, the determinant is not affected by the PMD.

Let F(ω) be the transfer matrix of the FSE given by the following:

${F(\omega)} = \begin{bmatrix} {F_{11}(\omega)} & {F_{12}(\omega)} \\ {F_{21}(\omega)} & {F_{22}(\omega)} \end{bmatrix}$ From the above, F(ω) can be rewritten as follows: F(ω)=P(ω)J ^(H)(ω) where P(ω) is a scalar linear factor that depends on G(ω) (and possibly the noise power for minimum mean-square error (MMSE) criteria), while the superscript “H” denotes transpose and conjugate.

The determinant of the equalizer transfer matrix is as follows: det{F(ω)}=P ²(ω)det{J ^(H)(ω)}=P ²(ω) Here, the determinant is not affected by the PMD. That is, the determinant is independent of PMD variation such as polarization rotation.

Let J(ω₀, t) and F(ω₀, t)=P(ω₀)J^(H)(ω₀, t) be the PMD matrix and the FSE transfer matrix at a given frequency ω₀ and instant t, respectively. For simplicity, the CD parameter is assumed to not change with time (i.e., P(ω₀, t)=P(ω₀)). The determinant can be defined as follows: S(ω₀ ,t)=det{F(ω₀ ,t)}=P ²(ω₀) Here, S(ω₀, t) is independent of PMD time variations.

Let F(ω₀, 0) be the transfer matrix at instant t=0. In the presence of a clock offset ΔT, the transfer matrix at instant t is as follows: F(ω₀ ,t)=e ^(−jω) ⁰ ^(τ) P(ω₀)J ^(H)(ω₀ ,t) where τ=ΔT/(T+ΔT)t<200×10⁻⁶t, with T being the symbol period. From the above, S(ω₀, t) is as follows: S(ω₀ ,t)=e ^(−j2ω) ⁰ ^(τ) S(ω₀,0) from which the determinant contains information of the sampling phase error.

Denoting |S(ω₀, t)|=K and taking into account the following: S(ω₀ ,t)=e ^(−j2ω) ⁰ ^(τ) S(ω₀,0) Note that ρ(ω₀, t) is as follow: ρ(ω₀ ,t)=S(ω₀ ,t)S*(ω₀,0)=K ² e ^(−j2ω) ⁰ ^(τ) Then, the phase error signal can be obtained from the following: ε_(ƒse)=−angle(ρ(ω₀ ,t))=2ω₀τ The sampling phase error is derived directly from the FFE taps, therefore it can be used even during a blind adaptation procedure. The phase error as defined previously can be used directly for timing recovery. Further note that P+I TR loop will avoid any FFE tap shifting (i.e., T→0).

In practical receivers, independent carrier recovery for each polarization can be used at the output of the FFE. In this case, the FFE taps for each polarization can be slowly rotated with arbitrary phases, as shown by the following: F(ω₀ ,t)=e ^(−jω) ⁰ ^(τ) e ^(jϕ(t)) P(ω₀)R(t)J ^(H)(ω₀ ,t) with the following:

${R(t)} = \begin{Bmatrix} {e\frac{{\phi_{x}(t)} - {\phi_{y}(t)}}{2}} & 0 \\ 0 & e^{\frac{- {j{({{\phi_{x}{(t)}} - {\phi_{y}{(t)}}})}}}{2}} \end{Bmatrix}$ ${\phi(t)} = \frac{{\phi_{x}(t)} + {\phi_{y}(t)}}{2}$ Here, R(t) is unitary and the phase of the determinant of F(ω₀, 0) varies with the rotations of the FFE taps, shown by the following: S(ω₀ ,t)=e ^(−j2ω) ⁰ ^(τ) e ^(j2ϕ(t)) S(ω₀,0)

Thus, the rotations of the equalizer taps impact the phase of the determinant of F(ω₀, 0); therefore, it cannot be used to provide reliable information of the sampling phase. However, in order to mitigate the impact of the taps rotation on the sampling phase estimation, S(ω₀, t) is defined as the determinant of the following matrix:

$\begin{matrix} {{M_{f}\left( {\omega_{0},t} \right)} = {{F\left( {\omega_{0},t} \right)}{F^{H}\left( {{- \omega_{0}},t} \right)}}} \\ {= {e^{{- j}\; 2\;\omega_{0}\tau}{{P\left( \omega_{0} \right)}}^{2}{R(t)}{J^{H}\left( {{- \omega_{0}},t} \right)}{R^{H}(t)}}} \\ {= {e^{{- j}\; 2\;\omega_{0}\tau}{{P\left( \omega_{0} \right)}}^{2}{Z\left( {\omega_{0},{- \omega_{0}},t} \right)}}} \end{matrix}$ where Z(ω₀, −ω₀, t) is a unitary matrix for all (ω₀, t). Thus, the taps rotation does not affect the phase of the determinant, which is shown as follows: S(ω₀ ,t)=det{M _(ƒ)(ω₀ ,t)}=e ^(−j4ω) ⁰ ^(τ) |P(ω₀)|⁴

Let F(Ω₀) be the transfer matrix of the discrete time FSE given by the following:

${F\left( \Omega_{0} \right)} = \begin{bmatrix} {F_{11}\left( \Omega_{0} \right)} & {F_{12}\left( \Omega_{0} \right)} \\ {F_{21}\left( \Omega_{0} \right)} & {F_{22}\left( \Omega_{0} \right)} \end{bmatrix}$ where Ω₀ is as follows:

$\Omega_{0} = {\omega_{0}\;\frac{T}{OS}}$ where OS is an oversampling factor.

Elements of F(Ω₀) can be evaluated as follows:

${F_{ab}\left( \Omega_{0} \right)} = {\sum\limits_{k = 0}^{N_{{FSE}^{- 1}}}{{f_{ab}(k)}e^{{- {jk}}\;\Omega_{0}}}}$ where ƒ_(ab)(k), a, bε[1,2] are the taps of the FSE and N_(FSE) is the number of taps.

If Ω₀ is set as follows:

$\Omega_{0} = {\pm \;\frac{\pi}{4}}$ then the filtering process is simplified for VLSI implementation.

Returning to the device architecture 200, an error evaluation or error computation module 250 is coupled to the ITR module 220. The error evaluation module can be configured to compute a slicer error and a first sampling phase error (SPE). The slicer error can be outputted to an LMS module, similar to LMS module 180 of FIG. 1. In order to provide a proper bandwidth for the TR loop, the sampling phase information derived from the FSE taps can be combined with a baud rate synchronization technique, such as one based on the Muller and Mueller (M&M) phase error. In a specific example, the first SPE is calculated according to a baud rate synchronization technique based on a M&M phase error, which can be represented by the following equation:

$ɛ_{m\; m} = {K_{m\; m}{\Re\left( {{\sum\limits_{{nN}_{p} + 2}^{{({n + 1})}N_{p}}{{{\hat{a}}^{*}(k)}{q\left( {k - 1} \right)}}} - {{{\hat{a}}^{*}\left( {k - 1} \right)}{q(k)}}} \right)}}$

-   -   where K_(mm), is a certain gain,     -   where         refers to real component of a complex number,     -   where N_(p) is a parallelism factor,     -   where q(k) is an input of slicer and error evaluation module,         and     -   where {circumflex over (α)}* is an output of the slicer and         error evaluation module.

In an example, a compression module 230 can be coupled between the ITR module 220 and the error computation module 250. The compression module 230 can be configured to compress the dual polarization input signal. Further, a slicer module 240 can be coupled to both the compression module 230 and the error computation module 250. The slicer module 240 can be configured to derive a data stream from the input signal. Those of ordinary skill in the art will recognize other variations, modifications, and alternatives.

In an example, the device 200 also includes a timing phase information (TPI) module 260, a combining module 270, and a timing recovery (TR) filter 280. The TPI module 260 can be coupled to the PMD equalizer module 210 or to an IFFT module that is coupled to the PMD equalizer module 210 (as described for the ITR module 220). The TPI module 260 can be configured to compute a second SPE from the plurality of PMD taps from the PMD equalizer module 210. Then, the combining module 270 can combine the first SPE and the second SPE into a total phase error (TPE). That is, the total phase error is ε_(t)=ε_(mm)+ε_(ƒse). The TR filter 280 can filter the TPE to be used by the ITR module 220 to synchronize the input signal.

The present invention provides for device structures and methods of computing sampling phase error according to the algorithms described previously. In a specific example, the TPI module computes the second SPE according to the following equation: ε_(ƒse) =−K _(ƒse)angle(det(M _(ƒ)))

-   -   where K_(ƒse)=[2⁻¹, . . . , 2⁻⁴], and     -   where M_(ƒ)=e^(−j2ω) ⁰ ^(τ)|P(ω₀)|²Z(ω₀, −ω₀, t),     -   where ω₀ is a given frequency,     -   where

${\tau = {\frac{\Delta\; T}{\left( {T + {\Delta\; T}} \right)t} < {200 \times 10^{- 6}t}}},$

-   -   where P(ω₀) is a CD parameter, and     -   where Z(ω₀, −ω₀, t) is a unitary matrix for all (ω₀, t).

In a specific example, the TPI module computes the second SPE according to the following equation: ε_(ƒse)=2ω₀τ

-   -   where ω₀ is a given frequency, and     -   where

${\tau = {\frac{\Delta\; T}{\left( {T + {\Delta\; T}} \right)t} < {200 \times 10^{- 6}t}}},$

-   -   where τ is a given time, and     -   where T is a symbol period.

In an example, the present invention provides a method of operating a coherent optical receiver device. The method can include providing an input signal; computing, by a first fast Fourier transform (FFT) module receiving the input signal, a first discrete Fourier transform (DFT) of the input signal. The method can include compensating, by a chromatic dispersion (CD) equalizer module coupled to the first FFT module, for CD affecting the input signal; and compensating, by a polarization mode dispersion (PMD) equalizer module coupled to the CD equalizer module and coupled to a least means square (LMS) module and having a plurality of PMD taps, for PMD affecting the input signal following the compensation by the CD equalizer module. Further, the method can include computing, by an inverse FFT (IFFT) module coupled to the PMD equalizer module, an inverse DFT of the input signal. In an example, the method includes filtering, by the LMS module coupled to the CD equalizer module and the second FFT module and the PMD equalizer module, the input signal.

In an example, the method includes computing a total sampling error from two sampling phase errors. More specifically, the method can include computing, by an error evaluation module coupled to the IFFT module, a first sampling phase error (SPE); and computing, by a timing phase information (TPI) module coupled to the error evaluation module and the IFFT module, a second SPE from the plurality of PMD taps. Then, the method includes combining, by a combining module coupled to the TPI module and the error evaluation module, the first and second SPE into a total phase error (TPE). Further, the method includes filtering, by a timing recovery (TR) filter coupled to an interpolated timing recovery (ITR) module and the combining module, the TPE. With the filtered TPE, the method includes synchronizing, by the ITR module, the input signal according to the TPE. Outside of the TR loop, the method includes computing, by a second FFT module coupled to the error evaluation module, a second DFT of the input signal, which is fed to the LMS module.

FIG. 3A-3D are simplified graphs illustrating simulations for a coherent optical receiver according to conventional example. As shown, graphs 301-304 illustrate a first test case applying the constrained adaptive algorithm or tap stabilizer algorithm. Here, the LMS step-size is 2⁻¹¹ and the clock offset is 0 ppm. FIG. 3A (graph 301) shows the signals at the FFE taps (i.e., PMD equalizer taps). FIG. 3B (graph 302) shows the sampling phase error computed from the PMD equalizer taps. FIG. 3C (graph 303) shows the clock error and FIG. 3D (304) shows an Rx constellation.

FIG. 4A-4D are simplified graphs illustrating simulations for a coherent optical receive according to an example of the present invention. As shown, graphs 401-404 illustrate a second test case with an unconstrained adaptive algorithm (i.e., without the tap stabilizer algorithm). The LMS step-size and clock offset are the same as for FIGS. 3A-3D (i.e., 2⁻¹¹ and 0 ppm, respectively). Similarly, FIG. 4A (graph 401) shows the signals at the FFE taps equalizer taps. FIG. 4B (graph 402) shows the sampling phase error computed from the PMD equalizer taps. FIG. 4C (graph 403) shows the clock error and FIG. 4D (404) shows an Rx constellation. Compared to the case of FIGS. 3A-3D, this case does not estimate the sampling phase error as accurately.

FIG. 5A-5D are simplified graphs illustrating simulations for a coherent optical receiver according to conventional example. As shown, graphs 501-504 illustrate a third test case applying the tap stabilizer algorithm with a time variant differential-group-delay (DGD). Here, the LMS step-size is 2⁻⁸ and the channel is characterized by DGD=T/2→Rot. KHz→DGD=T/2. FIG. 5A (graph 501) shows the signals at the FFE taps (i.e., PMD equalizer taps). FIG. 5B (graph 502) shows the sampling phase error computed from the PMD equalizer taps. FIG. 5C (graph 503) shows the clock error and FIG. 5D (504) shows an Rx constellation.

FIG. 6A-6D are simplified graphs illustrating simulations for a coherent optical receive according to an example of the present invention. As shown, graphs 601-604 illustrate a fourth test case with without the tap stabilizer algorithm with a time variant DGD. The LMS step-size and channel characterization are the same as for FIGS. 5A-5D (i.e., 2⁻⁸ and DGD=T/2→Rot. KHz→DGD=T/2, respectively). Similarly, FIG. 6A (graph 401) shows the signals at the FFE taps equalizer taps. FIG. 6B (graph 602) shows the sampling phase error computed from the PMD equalizer taps. FIG. 6C (graph 603) shows the clock error and FIG. 6D (604) shows an Rx constellation. Compared to the case of FIGS. 5A-5D, this case does not estimate the sampling phase error as accurately.

While the above is a full description of the specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention which is defined by the appended claims. 

What is claimed is:
 1. A coherent optical receiver device, the device comprising: a compensation module configured to receive an input signal, the compensation module having a plurality of taps; an evaluation module coupled to the compensation module, the evaluation module being configured to compute a first sampling phase error (SPE) from the input signal; a timing phase information (TPI) module coupled to the compensation module, the TPI module being configured to compute a second SPE from the plurality of taps; and a combining module coupled to the evaluation module and the TPI module, the combining module-being configured to combine the first and second SPE into a total phase error (TPE).
 2. The device of claim 1 wherein the input signal is a dual-polarization input with an x-type polarization input and a y-type polarization input.
 3. The device of claim 1 wherein the compensation module includes a non-adaptive frequency-domain (FD) equalizer, an adaptive FD equalizer, or both.
 4. The device of claim 1 wherein the first SPE is computed according to a baud rate synchronization technique based on a Muller and Mueller phase error.
 5. The device of claim 1 wherein the evaluation module includes a slicer module configured to derive a data stream from the input signal.
 6. The device of claim 1 further comprising a zero padding module coupled to the evaluation module and the compensation module, the zero padding module being configured to increase a sampling rate of the input signal.
 7. The device of claim 1 wherein the evaluation module includes a chromatic dispersion (CD) equalizer module receiving the input signal and being configured to compensate for CD affecting the input signal; wherein the evaluation module includes a polarization mode dispersion (PMD) equalizer module coupled to the CD equalizer module, the PMD equalizer having a plurality of PMD taps and being configured to compensate for PMD affecting the input signal; and wherein the plurality of taps includes the plurality of PMD taps.
 8. The system of claim 1 wherein the optical signal is a dual-polarization signal with an x-type polarization signal component and a y-type polarization signal component.
 9. The system of claim 1 wherein the compensation module includes a non-adaptive frequency-domain (FD) equalizer, an adaptive FD equalizer, or both.
 10. The system of claim 1 wherein the first SPE is computed according to a baud rate synchronization technique based on a Muller and Mueller phase error.
 11. The system of claim 1 wherein the evaluation module includes a slicer module configured to derive a data stream from the input signal.
 12. The system of claim 1 wherein the receiver device further comprising a zero padding module coupled to the evaluation module and the compensation module, the zero padding module being configured to increase a sampling rate of the input signal.
 13. The system of claim 1 wherein the evaluation module includes a chromatic dispersion (CD) equalizer module receiving the input signal and being configured to compensate for CD affecting the input signal; wherein the evaluation module includes a polarization mode dispersion (PMD) equalizer module coupled to the CD equalizer module, the PMD equalizer having a plurality of PMD taps and being configured to compensate for PMD affecting the input signal; and wherein the plurality of taps includes the plurality of PMD taps.
 14. An evaluation module device, the device comprising: a timing recovery (TR) module configured to receive a compensated input signal; a first sampling phase error (SPE) module coupled to the TR module and being configured to compute a first SPE; a second SPE module being configured to receive a plurality of taps signals and to compute a second SPE; and a combining module coupled to the first SPE module, the second SPE module, and the TR module; the combining module being configured to combine the first SPE and the second SPE into a total phase error (TPE); wherein the TR module is configured to synchronize the compensated input signal using the TPE.
 15. The device of claim 14 wherein the TR module includes an interpolated timing recovery (ITR) module and a TR filter; wherein the ITR module is configured to receive the compensated input signal; wherein the TR filter is coupled to the combining module and the ITR module, the TR filter being configured to receive the TPE from the combining module and to provide a filtered TPE to the ITR module; and wherein the ITR module is configured to synchronize the compensated input signal using the filtered TPE.
 16. The device of claim 14 wherein the first SPE module includes a compression module and an error computation module; wherein the compression module is coupled to the TR module and the error computation module, and the compression module is configured to compress the compensated input signal; wherein the error computation module configured to compute the first SPE from the compressed, compensated input signal.
 17. The device of claim 16 wherein the first SPE module further comprises a slicer module coupled to the compression module and the error computation module; wherein the slicer module is configured to derive a data stream from the compensated input signal; and wherein the error computation module is further configured to compute a slicer error from the data stream.
 18. The device of claim 16 wherein the second SPE module includes a timing phase information (TPI) module coupled to the combining module and configured to receive the plurality of taps signals; wherein the TPI module is configured to compute the second SPE from the plurality of taps signals.
 19. The device of claim 18 wherein the compensated input signal comprises an input signal compensated by a Chromatic Dispersion (CD) equalizer module and by a PMD equalizer module; and wherein the plurality of taps signals comprises a plurality of PMD taps signals.
 20. An optical communication system, the system comprising: an optical channel having a first end and a second end; a transmitter device coupled to the first end of the optical channel; a receiver device coupled to the second end of the optical channel, the receive device comprising: a compensation module configured to receive an optical signal from the transmitter device over the optical channel, the compensation module having a plurality of taps; an evaluation module coupled to the compensation module, the evaluation module being configured to compute a first sampling phase error (SPE); a timing phase information (TPI) module coupled to the compensation module, the TPI module being configured to compute a second SPE from the plurality of taps; and a combining module coupled to the evaluation module and the TPI module, the combining module being configured to combine the first and second SPE into a total phase error (TPE). 